1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which can be operated by low voltage.
2. Description of the Related Art
Power consumption of the semiconductor integrated circuit is mainly decided by the product of electrostatic capacity, operating voltage, and the operation frequency. The amount of the power consumption becomes proportion to the square of the operating voltage (power supply voltage). Therefore, lowering the operating voltage is very effective for lowering the power consumption of the semiconductor integrated circuit. Then, various methods have been developed for the low voltage operation of the semiconductor integrated circuit.
For instance, Tokkai-Hei08-181593 unexamined Japanese patent application indicates a semiconductor integrated circuit for decreasing its power consumption by supplying a minimum voltage which does not cause a malfunction operation at the critical path, which minimum voltage is detected and determined in advance by using a dummy circuit for the critical path of the semiconductor integrated circuit and a voltage regulator.
However, when the power supply voltage of the entire integrated circuit is lowered, the following problems are caused. If the power supply voltage is lowered, the delay time of each gate of the semiconductor and the delay time depending on the wiring capacity (load capacity) will increase while consumption current decreases. Especially, because accurate estimation of the wiring capacity (load capacity) is difficult, a relative timing skew is included in the delay time depending on the wiring capacity (load capacity). For instance, regarding a synchronized semiconductor integrated circuit, the synchronized operation based on standard clock among block modules is necessary for the normal correct operation. The clock skew among block modules can be a cause for serious malfunctioning. Clock wiring patterns are installed to various direction in various form, so that it is very difficult to match and cancel the slew to 0 accurately among entire blocks at the design stage in consideration of all load capacity correctly. If the power supply voltage is lowered under above mentioned status, the difference of the amount of the delay among blocks becomes large because of the collapse of the load balance, and it causes the malfunction operation.
Moreover, slew (slew of transient response) of the transmitted waveform becomes not steep in the designed circuit which uses a low speed gate. If the output waveform become dull, the timing design becomes remarkably complex because the influence for the delay time by the slew of the waveform become large when the threshold of an internal circuit changes by the fluctuation of the process condition.